A Survey on Pre-Silicon Automated Vulnerability Discovery for Processors

Abstract

Modern processors leverage advanced microarchitectural optimizations for performance and energy efficiency, yet these improvements also introduce both functional and non-functional security flaws. To address these threats, hardware fuzzing and hybrid verification frameworks have emerged as promising approaches to improve verification coverage and vulnerability discovery efficiency. This paper surveys pre-silicon automated vulnerability discovery techniques for processors. We analyze security threats and the limitations of traditional verification methods, then review representative studies on the core components of hardware fuzzing. Furthermore, we examine the integration of formal verification, information flow tracking, and large language models into hybrid fuzzing frameworks. Finally, we summarize the challenges and outline future research directions toward intelligent hybrid frameworks.