PARAYOSYS: Tail-Aware Partition-Based Parallel RTL Synthesis

Abstract

Open-source RTL synthesis still underuses multicore machines because backend optimization mixes local rewriting with global transformations. We present ParaYosys, a partition-based parallel RTL synthesis framework implemented inside Yosys. ParaYosys partitions flattened RTL, exports deterministic partition netlists, runs partition-local backends in worker processes, and stitches legal whole-design netlists. Under a post-flatten backend-only scope, a 24-partition configuration completes 22 of 23 public RTL benchmarks, reaches $5.96 \times$ speedup, and gives 1.38× median speedup. Larger public designs up to 483,682 flattened cells still reach $3.18 \times-5.37 \times$. The main finding is that structural balance poorly predicts backend cost: the median structural tail is $1.04 \times$, the median runtime tail is $5.34 \times$, and the worst per-benchmark cost-model gap is $352 \times$. Lightweight partition features improve critical-shard identification from 9.1% to 45.5%, and cost-aware weighting reduces parallel wall time on 8 of 10 controlled reruns. Successful P24 cases pass CEC, with small median mapped QoR drift.