Function-Aware VLSI Partitioning for GNN-Based Hardware Trojan Detection

Abstract

Graph neural networks (GNNs) have shown strong potential for gate-level hardware Trojan detection, yet scalability remains a fundamental challenge. As integrated circuits grow in scale, existing GNN-based methods suffer from limited scalability and reduced discriminative power due to inherent constraints of message passing. Circuit partitioning offers a practical solution, but prior approaches target physical design’s area and timing closure or multi-FPGA emulation’s communication minimization and load balancing, overlooking the need to preserve functional structure. To address this gap, we model circuits as hypergraphs and propose FaHyPar, a functional-aware VLSI partitioning framework. We introduce the Functional Independence Ratio (FIR), which combines hypergraph connectivity with a correction term derived from circuit-level priors to better capture functional relationships. We further identify performance bottlenecks in large-scale partitioning and optimize the algorithm through three-stage parallelization. Experimental results demonstrate that the proposed method improves the functional awareness of subcircuits and significantly enhances downstream GNN-based detection on large-scale gate-level designs in acceptable overhead.