Aug 2026· IEEE Non-Volatile Memory System and Applications Symposium· pp. 1-6· 0 citations· 16 references
Abstract
Hybrid flash storage combines large-capacity highdensity flash memory with high-performance low-density flash memory, providing excellent cost-effectiveness. Existing data placement strategies for hybrid flash storage typically employ hotness-based data migration relying on a twotier architecture. This approach not only overlooks the variations in read retry counts across different reliability stages, but also leads to severe capacity degradation and exacerbated write amplification. To address these issues, we propose RARO, a Reliability-Aware Read performance Optimization scheme for hybrid flash storage. RARO redesigns data placement by leveraging application-level data access patterns and device-level flash reliability. This is achieved by dynamically migrating data based on its retry count and access hotness. Data residing in an unsuitable flash type triggers immediate migration, with higher priority given to data exhibiting both high retry counts and hotness for placement into low-density flash, thereby enabling proactive performance optimization. Furthermore, RARO employs a progressive threetier (SLC-TLC-QLC) management framework to mitigating the capacity loss. The evaluation of RARO, conducted on the FEMUbased emulator, significantly enhances read performance, with IOPS reaching 9.46× to 15.9× of the baseline across different aging stages, while also recovering 57% to 92% of the usable device capacity.
FlashAccel integrates HBF into HBM-based GPUs, providing architectural support to mitigate access latency and introduces an HBF-aware storage management layer together with a programming model to organize persistent data in HBF and coordinate heterogeneous memory resources at the system level.
Xinyu Wang, Yalong Xue, Xiaotian Sun et al.· 1 citation
FLINT is proposed, a workload-driven HBF substrate for capacity-scalable LLM inference that integrates HBF as a memory-capacity tier alongside HBM while addressing three adoption challenges.
Geraldo F. Oliveira, Arash Tavakkol, Xiang-Yu Zhu et al.· 1 citation
A Lightweight Cache Buffer Management (LCBM) strategy that avoids precise frequency tracking altogether and reduces the average read latency and the write response time, while eliminating the metadata overhead of counter- and LRU-based designs is introduced.
Thanks to notable performance and capacity advantages, NVMe SSDs promise an effective cache tier for alleviating the load pressure of back-end storage servers. Compared with DRAM, an NVMe SSD exhibits up to hundreds of times larger capacity but delivers two orders of magnitude smaller bandwidth per gigabyte. This paper...
This work proposes a high-performance NAND flash-based ISC architecture with enhanced activation buffering, and introduces a distributed dataflow approach for the NAND-PIM array that maximizes computational parallelism by employing efficient intra-plane data mapping.
Sanghun Shin, Sangyeon Kim, Gisan Ji et al.· 0 citations
An enhancement to the Clean First LRU (CFLRU) algorithm, termed Dirty Hot Clean Hot CFLRU (DCH-CFLRU), which provides both clean and dirty pages with a second chance, and exhibits better overall flash memory performance and extending its lifespan.
Panch Dev Bhatta, S. R. Joshi, A. Saud· Journal of Physical and Life...· 0 citations
We use cookies to run the site and, with your consent, for analytics and to show ads.
See our Cookie Policy.