Urania: Unleashing the Potential of Adaptive RNS for Fully Homomorphic Encryption Acceleration

Abstract

With the growing adoption of fully homomorphic encryption (FHE), improving its computational efficiency has become a key research focus, and designing dedicated accelerators remains an effective approach. Existing FHE accelerators achieve high performance but are often constrained by empirical design tendencies that favor small-bitwidth hardware and rely on fixed small-bitwidth RNS decomposition. Recent advances in FHE compilation and modular multiplication acceleration, however, demonstrate performance benefits from delayed rescaling and large-bitwidth execution. This motivates a reconsideration of whether traditional fixed small-bitwidth designs are optimal for FHE acceleration. In this work, we explore the potential of adaptive RNS bitwidth for FHE accelerators by combining compiler-guided optimization with highly reconfigurable, variable-bitwidth hardware that incorporates lookup-table strategies. This hardware-software co-design enables efficient bitwidth exploration and improves acceleration efficiency. Experimental results show: (1) up to 1.68× and 1.54× speedup over SOTA accelerators Trinity and SHARP; (2) 10.7–19.8× improvement in EDAP compared to Trinity; (3) over 33% reduction in chip area compared to SOTA accelerators.