Control Flow Defense Technology for RISC-V Based on Encrypted Shadow Stacks

Abstract

RISC-V instruction set architecture plays an important role in embedded systems with its characteristics of open source, free and modular design. However, it is susceptible to code reuse attacks due to the lack of memory protection mechanisms. For this reason, the paper proposes a design scheme for encrypted shadow stack (ESS) based on RISC-V custom instruction extension. It utilizes a lightweight Feistel structure to provide encryption protection for return address and stack pointer during function calls, storing the copy in memory in the form of ciphertext. Before the function returns, the ciphertext copy is prefetched and decrypted, then compared with the original data in the function stack to achieve fast verification of control flow integrity. Rocket custom coprocessor (RoCC) operates in parallel with the main processor to hide the latency caused by encryption, decryption, and memory access operations, thereby ensuring the efficiency of program execution. The experiment achieved RoCC extension of ESS in Rocket chip and generated a simulator to simulate the test program. The result indicate that the scheme can effectively detect and prevent tampering attacks on return address and stack pointer. The average execution time cost of introducing ESS is 1.27%. All hardware overheads remain below 3.5% after extending RoCC. The proposed solution provides a secure, efficient, and low-cost implementation approach for RISC-V control flow integrity.