FPGA-Based Implementation of a Multi-Operation 4-Bit Arithmetic Logic Unit
Abstract
Abstract: Arithmetic Logic Units (ALUs) are fundamental building blocks of modern digital systems, responsible for executing arithmetic and logical operations within processors, controllers, and embedded computing platforms. This paper presents the design and FPGA-based implementation of an enhanced 4-bit Arithmetic Logic Unit (ALU) using Verilog Hardware Description Language (HDL). Unlike conventional 4-bit ALUs that typically support a limited set of arithmetic and logical functions, the proposed architecture incorporates eight distinct operations, namely addition, subtraction, multiplication, XOR, AND, OR, increment, and decrement. The operation selection is controlled through a 3-bit control signal, enabling efficient execution of multiple functions within a single hardware module.The ALU accepts two 4-bit input operands and generates an 8-bit output to accommodate arithmetic operations such as multiplication, which can produce results up to 8 bits in length. The design was developed at the Register Transfer Level (RTL) and verified through functional simulation to ensure accurate operation under all possible control conditions. A total of 256 input combinations were evaluated for each operation, resulting in comprehensive validation across 2,048 test scenarios. Simulation results confirmed 100% functional correctness for all implemented operations with zero observed logical errors. The synthesized design demonstrated low resource utilization, requiring fewer than 50 logic elements on a target FPGA device while operating at a maximum clock frequency exceeding 150 MHz. The proposed ALU achieves enhanced computational capability without significant increases in hardware complexity, making it suitable for low-cost FPGA implementations, educational processor designs, embedded systems, and digital signal processing applications requiring compact and efficient arithmetic computation. Keywords: FPGA, Arithmetic Logic Unit (ALU), Verilog HDL, Digital Design, RTL Implementation.