Topology-Aware Deep Reinforcement Learning for VLSI Floorplanning via Graph Attention Feature Fusion

Abstract

VLSI floorplanning is a critical electronic design automation stage burdened by a vast search space. Traditional heuristics struggle with computational efficiency, while existing machine learning methods often fail to sufficiently capture complex netlist topologies. To address these limitations, we propose a topology-aware deep reinforcement learning framework for VLSI floorplanning. At the core of our architecture is a state encoder utilizing multi-head Graph Attention Networks (GAT) for hierarchical feature extraction. By fusing raw macro geometric properties with dynamically aggregated topological embeddings, the model generates an enhanced state representation. This representation guides a two-stage decoding mechanism, which pairs a Pointer Network for sequential macro floorplanning with an auxiliary Bernoulli-sampled head for discrete rotation decisions. Furthermore, we integrate a Just-In-Time (JIT) accelerated Skyline heuristic to enable rapid layout legalization and efficient composite reward calculation. Experimental results on GSRC benchmarks demonstrate that our framework achieves a 100% fixed-outline success rate, matching existing learning-based models, while reducing the average half-perimeter wirelength (HPWL) by 32.4% and improving area utilization.