FROM PMOS TO CFET: A COMPREHENSIVE SYSTEMATIC REVIEW AND COMPARATIVE ANALYSIS OF MOSFET-BASED DEVICE ARCHITECTURES FOR NEXT-GENERATION VLSI SYSTEMS

Abstract

The relentless drive toward transistor miniaturization that has sustained Moore's Law for over five decades has forced the semiconductor industry through a succession of device-architecture transitions, each addressing the electrostatic and parasitic limitations of its predecessor. This paper presents a systematic review and comparative analysis of MOSFET-based device architectures spanning the foundational planar PMOS/NMOS transistor and complementary metal-oxide-semiconductor (CMOS) circuit, the FinFET/tri-gate transition commercialized in 2011, gate-all-around (GAA) nanowire and Nano sheet field-effect transistors now in high-volume manufacturing, the fork sheet architecture, and the emerging complementary FET (CFET). Technical literature and primary industry disclosures from IEEE Xplore, arXiv, and semiconductor foundries and research consortia (imec, Intel, TSMC, Samsung) covering 2011–2026 were reviewed and synthesized using a PRISMA-inspired methodology adapted for engineering and technology sources. Each architecture is evaluated against a consistent set of criteria: gate electrostatic control, short-channel-effect suppression, area and density scaling, power–performance trade-offs, and manufacturing readiness, and the findings are consolidated into a comparative summary table. The review finds that GAA nanosheet transistors have now entered high-volume production across three major foundries, while the CFET architecture — in which n-type and p-type devices are stacked vertically — is positioned as the leading contender to extend logic scaling into the sub-1 nm regime, contingent on resolving wafer-bonding, contact-yield, and thermal-crosstalk challenges. The paper concludes with an assessment of open research gaps and beyond-CFET directions, including two-dimensional channel materials and monolithic three-dimensional integration.