A generalized parallelization algorithm for particle-in-cell simulations

Abstract

Particle-in-cell (PIC) codes are a cornerstone of plasma-based accelerator research. We present a generalized parallelization algorithm for PIC simulations that achieves high efficiency across modern high-performance computing (HPC) architectures, including CPUs (x86 and Arm) and graphics processing units (GPUs) (NVIDIA, AMD). The algorithm employs a micro-spatial domain decomposition combined with a high-performance particle manager for efficient particle migration between domains. Each domain is mapped to a CPU thread or GPU thread block, ensuring balanced parallel workloads even in realistic scenarios. Implementations use architecture-specific programming models—OpenMP for CPUs and CUDA/HIP for GPUs—while maintaining a common algorithmic structure, making porting straightforward. Benchmark results for a representative 2D problem demonstrate excellent performance on both single devices and large-scale HPC systems. The algorithm is also show to be extendable for other PIC variants and architectures.