This work identifies homomorphic multiplication as the most error-sensitive operation in practical HE pipelines and characterize how faults propagate and amplify through it, exposing a critical robustness vulnerability and motivating the need for more resilient HE deployments.
Abstract
Homomorphic Encryption (HE) enables computation on encrypted data without decryption and is a key primitive for privacy-preserving computation in sensitive domains such as healthcare, finance, and government. Its security relies on noise injection, which introduces intrinsic error sensitivity and raises concerns about the fault tolerance of HE systems, as hardware- and software-induced faults can evade traditional detection mechanisms and lead to silent data corruption. In this work, we analyze the sensitivity of HE to bit-level faults, focusing on the CKKS (Cheon--Kim--Kim--Song) scheme widely used for approximate arithmetic in AI and machine learning workloads. We identify homomorphic multiplication as the most error-sensitive operation in practical HE pipelines and characterize how faults propagate and amplify through it, exposing a critical robustness vulnerability and motivating the need for more resilient HE deployments.
It is shown that both the timing and the location of errors in the ciphertext components \(c_0\) and \(c_1\) have a significant impact on the correctness of the final FHE output.
Vattana Chan, Matías Mazzanti, Karthik Swaminathan et al.· 0 citations
This work presents an efficient fault-tolerance scheme for CPU-based CKKS computation that achieves a 100 percent empirical detection rate across 150,000 non-crashing corrupted-result cases and maintains application accuracy close to the fault-free baseline over a wide range of fault rates.
Jia-Nan Mu, Ge Yu, Tenghui Hua et al.· arXiv.org· 0 citations
S2MM is presented, the first scalable FPGA-based accelerator designed for HE MM, and a novel datapath for Homomorphic Linear Transformation (HLT), the dominant workload in HE MM is proposed, enabling fine-grained on-chip data reuse and substantially reducing both off-chip memory traffic and on-chip memory demand.
Zhi-Han Xu, Rajgopal Kannan, Viktor K. Prasanna· ACM Transactions on Reconfig...· 0 citations
HPCC is presented, the first low-latency 3-input multiplication gadget for arbitrary fields that maintains a constant latency of one cycle, independent of the number of shares, and is leveraged to implement the first composable AES S-Box with two cycles of latency with an arbitrary number of shares.
Frederik Reiter, A. Moradi· IACR Cryptology ePrint Archi...· 0 citations
This paper investigates cold boot attacks against NTRU-based signature scheme Falcon and its ancestor, the signature scheme of Ducas–Lyubashevsky–Prest (DLP), and proposes countermeasures with negligible computational cost that significantly reduce the memory footprint of signing keys for Falcon and DLP, and at the sam...
This work presents an optimized software implementation providing 1 st -order side-channel protection, as well as the first efficiency-oriented 2 nd -order implementation, surpassing previous solutions in performance.
Juan Moreno-Cenizo, Eros Camacho-Ruiz, M. Martínez-Rodríguez et al.· International Conference on...· 0 citations
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