Design and Implementation of 8-Bit Low-Power ALU Using Power Gating on Artix-7 FPGA Board

Abstract

Portable electronics, Internet of Things (IoT) technology and edge AI are all examples of the many technologies that have seen rapid growth in recent years, which have significantly boosted the need for energy-efficient digital circuits. The Arithmetic Logic Unit (ALU) consumes a lot of power because of the constant switching on and off and leakage currents. This paper presents the design and implementation of an 8-bit low-power ALU using the power gating technique to minimise static power loss and leakage power loss. The new architecture features sleep transistors that switch off the ALU when it isn't in use. This method reduces the leakage current while still maintaining functional precision in active operation. The ALU can execute eight arithmetic and logical operations, including add, subtract, AND, OR, XOR, NOT, increment, and decrement. The design is implemented in a Xilinx Artix-7 FPGA, designed with Verilog HDL and simulated with the Vivado Design Suite. Functional verification is performed via simulation, and synthesis and implementation are performed to evaluate power, resources and timing performance. The power-gated ALU has significantly lower static power consumption and similar operating frequency and hardware overhead when compared with a conventional ALU design. This design is an effective and scalable approach to power-consumption-critical VLSI applications, such as battery-powered embedded processors, IoT, wearable electronics, and power-efficient computing platforms.