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Conference

Scattering-center parameter-driven FPGA-based wideband radar echo real-time simulation

Sep 2026 · International Conference on Optics, Electronics, and Communication Engineering · Vol 14349, pp. 1434906 - 1434906-11 · 0 citations · 14 references
Engineering

Abstract

In high-resolution inverse synthetic aperture radar (ISAR) echo simulation, wideband conditions and three-dimensional target geometry induce strong frequency-angle coupling and rapid time-varying characteristics among the delay, amplitude, and phase of individual scattering centers. Target micro-motion further introduces Doppler broadening and migration through range cells (MTRC), imposing stringent requirements on amplitude-phase coherence, temporal consistency, and real-time throughput. Existing approaches either rely on narrowband or two-dimensional approximations that yield insufficient cross-band coherence, employ full-wave electromagnetic computation that cannot meet engineering real-time constraints, or perform compensation only in post-processing without guaranteeing the intrinsic correctness of the generated signals. To address these challenges, this paper presents a scattering-center parameter-driven FPGA-based wideband radar echo real-time simulation method. In the proposed approach, triplets of {delay, amplitude, phase} parameters for each scattering center at every pulse are pre-computed on the host and loaded into on-chip Block RAM via PCIe. A dual-buffer parameter paging mechanism, a five-stage pipelined 16-bit fixed-point complex multiplier, and a multi-channel delay-triggered superposition engine are implemented on the FPGA to perform precise integer-sample delay scheduling, per-sample complex weight modulation, and coherent summation at a 2 GHz sampling rate. The synthesized echoes are streamed back to the host via a PCIe interface. The system is synthesized and implemented on an FPGA. RTL simulation and system-level tests demonstrate that the generated LFM waveforms satisfy the design specifications in terms of pulse width and bandwidth errors. The two-dimensional raw data correlation coefficient between the FPGA output and the reference model exceeds 0.99, and the peak sidelobe ratio (PSLR) and integrated sidelobe ratio (ISLR) after range compression are close to the theoretical values. Focused imaging results exhibit no noticeable artifacts, validating the generation-end coherence consistency and engineering feasibility.

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