Resource-Efficient Accurate and Approximate Signed Multipliers based on Boolean Restructuring and LUT Encoding

Abstract

Multiplication is a fundamental arithmetic operation used in various signal processing applications, like image and video processing. Many FPGA vendors provide high-performance DSP-based multipliers as part of their offerings. However, these are limited in number and hardwired within the FPGA fabric, potentially introducing additional routing delays. To address this, FPGA vendors also offer optimized soft IP cores for multiplication that are flexible and provide many performance benefits. However, these soft multiplier IP cores still require improvements to enhance resource efficiency and performance. This paper presents resource-optimized, high-performance, power-efficient, accurate, and approximate softcore signed multiplier architectures for Xilinx FPGAs. These architectures make optimal use of fundamental FPGA elements, such as LUTs and Carry4 primitives, by translating the Boolean network of the multiplier into an optimal/near-optimal LUT-Carry4 netlist, thereby minimizing overall critical path delay and resource utilization. Compared to the speed-optimized 8-bit Xilinx IP multiplier, the proposed accurate multiplier shows improvements of 38.36% in LUT utilization and 71.96% in PDRP. Furthermore, the proposed approximate multiplier achieves greater hardware savings and lower critical path delays than the best existing designs with similar accuracy.