Resource-Efficient FPGA Implementation of Bitonic Sorting Networks with Block-Parallel Search

Abstract

Sorting is a basic operation in contemporary computer systems, and is important to applications like databases, information retrieval, signal processing, real-time data analytics, and more. Traditional CPU and GPU sorting methods can struggle with latency, memory bandwidth requirements, and power efficiency, especially as data is increasingly used in high-performance applications. For many data processing applications, high performance and low power consumption are crucial, and Field-Programmable Gate Arrays (FPGAs) provide an ideal solution for sorting. In this paper, a resource-efficient FPGA-based Bitonic Sorting Network with a hybrid search engine for searching and sorting simultaneously are presented. The proposed architecture takes advantage of parallel compare-and-swap operations, pipelining, and optimized memory usage to get highperformance operations while keeping the hardware overhead low. The design, implemented on a Xilinx Artix-7 FPGA in Verilog HDL, requires merely 880 Look-Up Tables (LUTs), 598 flip-flops and 0.104 W of power. The experimental results indicate a throughput of up to 136 M elements/s and a latency of 0.047ms, making the architecture appropriate for data-processing applications, such as embedded systems, FPGA accelerators, and real-time edge computing applications, that demand efficient and cost-efficient data processing.