Joint Optimization of Spatial Locality and Endurance for MAGIC with Capacity Constraints

Abstract

Memristor-Aided Logic (MAGIC), as a stateful logic paradigm for in-memory computing, has been widely explored in the field of memristive logic synthesis in recent years. However, existing methods primarily focus on the optimization for area and latency under an ideal single-array mapping scenario, which overlooks the impact of cross-array execution overhead and device endurance degradation caused by capacity-constrained array settings in practical implementations. To address these issues, this paper proposes a mapping method that jointly considers spatial locality and write balancing. For cross-array execution overhead, a locality-aware cost function is constructed, which enables the selection of spatially favorable candidate arrays and thereby reduces the number of arrays that each logic gate traverses when performing calculations. To address device endurance degradation, a write-balancing cost function is further introduced by jointly considering node lifetime and the wear level of each memristor device, so as to suppress the continued deterioration of hotspot cells. The proposed techniques are integrated into mainstream open-source memristive logic synthesis frameworks and evaluated on the ISCAS’85 benchmark suite. Experimental results show that, compared with the state-of-the-art frameworks SIMPLER and LV-MAGIC, the average number of crossed arrays per gate is reduced by 25.0% and 18.0%, while the normalized lifetime metric is improved by 1.44× and 1.35×, respectively.