Quantum at the Edge: Scalable Standalone FPGA Emulator for QAOA-Based Weighted-MaxCut

Abstract

Quantum computing (QC) emulation is critical for exploring and advancing near-term quantum algorithms, given the ongoing scalability and reliability challenges of quantum hardware. While FPGA-based QC emulators have emerged as efficient alternatives to bridge the gap toward practical quantum computers, most existing solutions depend on high-performance systems, limiting their applicability in embedded and edge environments. In this work, we present a scalable, standalone FPGA-based emulator specialized for resource-constrained systems. Our design targets the Quantum Approximate Optimization Algorithm (QAOA), particularly for the Weighted-MaxCut problem. By leveraging diagonal decomposition and a pipeline-centric hardware architecture, we reduce the computational complexity of QAOA from <inline-formula><tex-math notation="LaTeX">$\boldsymbol{O(N^{2})}$</tex-math><alternatives><mml:math><mml:mi mathvariant="bold-italic">O</mml:mi><mml:mo stretchy="false" mathvariant="bold">(</mml:mo><mml:msup><mml:mi mathvariant="bold-italic">N</mml:mi><mml:mrow><mml:mn mathvariant="bold">2</mml:mn></mml:mrow></mml:msup><mml:mo stretchy="false" mathvariant="bold">)</mml:mo></mml:math><inline-graphic xlink:href="lee-ieq1-3724836.gif"/></alternatives></inline-formula> to <inline-formula><tex-math notation="LaTeX">$\boldsymbol{O(N)}$</tex-math><alternatives><mml:math><mml:mi mathvariant="bold-italic">O</mml:mi><mml:mo stretchy="false" mathvariant="bold">(</mml:mo><mml:mi mathvariant="bold-italic">N</mml:mi><mml:mo stretchy="false" mathvariant="bold">)</mml:mo></mml:math><inline-graphic xlink:href="lee-ieq2-3724836.gif"/></alternatives></inline-formula>, where <inline-formula><tex-math notation="LaTeX">$\boldsymbol{N}$</tex-math><alternatives><mml:math><mml:mi mathvariant="bold-italic">N</mml:mi></mml:math><inline-graphic xlink:href="lee-ieq3-3724836.gif"/></alternatives></inline-formula> <inline-formula><tex-math notation="LaTeX">$\boldsymbol{=}$</tex-math><alternatives><mml:math><mml:mo mathvariant="bold">=</mml:mo></mml:math><inline-graphic xlink:href="lee-ieq4-3724836.gif"/></alternatives></inline-formula> <inline-formula><tex-math notation="LaTeX">$\boldsymbol{2^{n}}$</tex-math><alternatives><mml:math><mml:msup><mml:mn mathvariant="bold">2</mml:mn><mml:mrow><mml:mi mathvariant="bold-italic">n</mml:mi></mml:mrow></mml:msup></mml:math><inline-graphic xlink:href="lee-ieq5-3724836.gif"/></alternatives></inline-formula> is the state dimension for <inline-formula><tex-math notation="LaTeX">$\boldsymbol{n}$</tex-math><alternatives><mml:math><mml:mi mathvariant="bold-italic">n</mml:mi></mml:math><inline-graphic xlink:href="lee-ieq6-3724836.gif"/></alternatives></inline-formula> qubits. This reformulation and its architectural co-design significantly reduces hardware overhead, enabling larger qubit configurations on edge-level FPGAs. We encapsulate these optimizations into a hardware accelerator called the <italic>Quantum MaxCut Accelerator</italic> (QMA), which integrates seamlessly into a RISC-V platform, forming a self-contained emulator. Additionally, we introduce <italic>QC Emulator eXpress</italic> (QEX), a full-stack automation framework that streamlines QMA integration into configurable RISC-V platforms, significantly facilitating rapid and scalable emulator development and deployment. Through extensive prototyping of various QAOA emulators, our experiments confirm that the proposed QMA achieves energy reductions of up to <inline-formula><tex-math notation="LaTeX">$\textbf{907}\boldsymbol{\times}$</tex-math><alternatives><mml:math><mml:mtext mathvariant="bold">907</mml:mtext><mml:mo mathvariant="bold">×</mml:mo></mml:math><inline-graphic xlink:href="lee-ieq7-3724836.gif"/></alternatives></inline-formula> compared to the CPU-only software baseline under the same standalone FPGA/RISC-V setting and reliably supports up to 9 qubits on a mid-tier FPGA. These results demonstrate the energy efficiency and scalability of the proposed system as a self-contained FPGA/RISC-V platform for edge-local QAOA emulation, prototyping, and HW/SW co-design exploration under resource-constrained conditions.