BHARAT-TPM: Design and ASIC Implementation of an SPI Based AXI Enabled RSA-4096 Accelerator

Abstract

Trusted Platform Modules (TPMs) serve as hardware roots of trust in secure System on Chip (SoC) environments, supporting essential security services such as secure key exchange, digital signatures, authentication, and cryptographic key management. Public key cryptographic algorithms such as the Rivest Shamir Adleman (RSA) are fundamental to these operations, requiring efficient hardware implementations and communication interfaces. However, standalone pre-integration validation of AXI based cryptographic accelerators through a serial interface remains unaddressed in existing literature. This paper presents a deterministic, reusable hardware validation framework for AXI based cryptographic IP cores, realized as a structured, packet based SPI to AXI validation architecture. The proposed architecture employs dual clock domain synchronization and FIFO based buffering to ensure reliable data transfer between the SPI interface and the AXI enabled RSA-4096 accelerator. The architecture supports encryption, decryption, signature generation, and signature verification using an iterative Montgomery multiplication based modular exponentiation approach. The design is implemented in Verilog HDL and verified using standard cryptographic test vectors, validated on the Xilinx Virtex UltraScale VCU118 FPGA achieving 58.824 MHz with 52389 slices. The design further serves as a hardware verification platform within the RISC-V based BHARAT-TPM for validating AXI based cryptographic accelerator cores.