Research on the comprehensive management simulation case of integrated unmanned aerial vehicle systems
Abstract
With the rapid evolution of unmanned aerial vehicles (UAVs) toward higher autonomy and integrated multitasking capabilities, onboard main control chips are facing unprecedented computational demands. Accordingly, processor architectures are gradually shifting from traditional in-order execution designs to more sophisticated out-of-order (O3) architectures that provide higher instruction-level parallelism. In this context, accurately identifying and analyzing architectural performance bottlenecks in complex application scenarios has become a critical prerequisite for early-stage architecture design. However, existing performance evaluation platforms are often highly customized; they either lack cycle-accurate simulation capabilities at the microarchitectural level or do not support the execution of full operating systems such as Linux. As a result, they are insufficient for system-level architectural exploration of modern onboard chips. To address these challenges, this paper develops a cycle-accurate, microarchitecture-configurable simulation platform for UAV main control processors based on the gem5 framework, with full-system (FS) support. A parameterized microarchitectural template mechanism is introduced to enable flexible exploration of processor performance under different architectural configurations. Using this platform, a representative ARM Cortex-A76-style architecture is evaluated in a Linux OS environment with a diverse set of benchmarks covering different computational characteristics. System-level performance is analyzed using key metrics such as IPC and CPI, together with an in-depth investigation of microarchitectural events, including multi-level cache behavior and multi-core performance characteristics. Experimental results demonstrate that the proposed platform effectively captures the performance characteristics of different workloads in both computation and memory access, providing a reliable simulation tool and theoretical foundation for the future microarchitectural evolution and engineering design of UAV onboard processors.