An Evolutionary Optimization Framework for Robust Current Mirror Designs

Abstract

This paper presents a modular evolutionary optimization framework for the robust synthesis of analog circuits, with a focus on current mirrors. Unlike traditional approaches that rely heavily on designer expertise, the proposed framework automates the device sizing while accounting for process variations and mismatch in nanometer CMOS technologies. To improve the reliability of fitness evaluation under limited Monte Carlo sampling, an adaptive refinement strategy selectively increases the number of samples for promising candidates, reducing the likelihood of overestimated solutions while maintaining low computational cost. Additional strategies, including result caching and layout-aware constraints (e.g., common-centroid compatibility), further improve efficiency and feasibility. The framework is validated on simple and cascode current mirrors in a 130 nm process. All target specifications, including mismatch error below 0.5%, bandwidth above 10 MHz and output resistance above $30 \mathrm{k} \Omega$, are satisfied, demonstrating effective and robust automated design.