BHARAT-TPM: Micro-Architecture Design of AXI Enabled SM3 Hardware Accelerator for a RISC-V Trusted Platform Module

Abstract

Trusted Platform Modules (TPMs) are widely used in modern digital systems to provide a Root-of-Trust and support for various security applications. One of the cryptographic hash functions that is used in a TPM is Shang Mi 3 (SM3), which is standardized for use in commercial cryptography in China. With increasing demand for high-speed and low-power cryptographic systems, extensive research has focused on efficient micro-architecture implementations of SM3. This work presents an iterative SM3 hardware architecture integrated into the AXIbased BHARAT-TPM SoC, enabling support for TCG HASH commands. The proposed architecture achieves an efficient hardware implementation while maintaining compliance with the SM3 specification. Key design aspects including message expansion, compression function implementation, and iterative processing architecture are discussed. The design has been verified and implemented on a Xilinx Virtex Ultrascale+ VCU118 FPGA platform. The proposed architecture demonstrates a balanced area-performance tradeoff with a frequency of 286 MHz and a throughput of 2288 Mbps.