HPQEA: A Scalable FPGA‐Based High‐Performance Quantum Emulator With Parallel Architecture and High‐Bandwidth Memory Optimization

Abstract

In recent years, quantum emulation has attracted increasing attention as a practical approach for developing and evaluating quantum algorithms. However, existing solutions often face challenges in achieving broad applicability, high performance, and efficient utilization of hardware resources and memory. To address these limitations, this paper presents the high‐performance quantum emulation accelerator (HPQEA), a hardware architecture based on the state‐vector emulation approach. The proposed design incorporates four key techniques: a strict data storage strategy, a superior flexible processing element network, an optimized and parallelized CX swapper, and a high‐bandwidth memory‐based bulk data transfer engine. Implementation and evaluation on the Alveo U280 FPGA platform demonstrate that HPQEA can emulate quantum circuits efficiently while maintaining high fidelity and low mean square error. Experimental results show that for QFT benchmarks, HPQEA achieves up to 21,093 faster execution than the NVIDIA A100 GPU for circuits with fewer than 20 qubits. Moreover, the comparison with FPGA‐based related works shows promising results with significant speedup in terms of normalize gate speed from 2.77 to 1448.37. In addition, the architecture demonstrates strong energy efficiency, reducing power consumption by up to 15.58 compared to the Intel i9‐10940X CPU and 80.83 compared to the GTX 1080 GPU. These results highlight the scalability, efficiency, and practicality of HPQEA as a hardware platform for accelerating quantum algorithm emulation.