Measurement-Oriented Power Quality Disturbance Classification Using a Memory-Centric FPGA Architecture

Abstract

This article presents a measurement-oriented and hardware-aware memory-centric field-programmable gate array (FPGA) architecture for real-time, gap-free window-level power quality disturbance (PQD) classification at the grid edge. The proposed prototype performs deterministic postwindow classification on continuously acquired nonoverlapping 1024-sample windows, corresponding to 200 ms at 5.12 kHz; therefore, it is a streaming window-based single-label classifier rather than a sample-by-sample event detector. The system combines a pipelined Goertzel-based feature-extraction front-end with LightGBM inference driven by block random access memory (BRAM) and jointly optimizes compact feature representation, fixed-point quantization, model constraints, and memory organization for low-cost deployment. The trained tree model is transformed into BRAM-resident instruction streams for class-parallel inference without using digital signal processor (DSP) slices. Implemented on a Xilinx Artix-7 XC7A35T FPGA, the proposed architecture achieves 99.07 % classification accuracy over ten PQD categories. After each analysis window has been acquired, the complete postwindow processing latency is 35.54 $\mu $ s, including 4.24 $\mu $ s for classification, which is far shorter than the 200 ms window duration and enables continuous gap-free window processing. The implementation uses only 32 DSP slices in total. Including the observation window, the decision time from the beginning of a nonoverlapping window is approximately 200.036 ms. These results demonstrate that memory-centric tree execution provides a practical and low-cost FPGA solution for real-time, gap-free window-level power quality (PQ) monitoring at the grid edge.