Design and Implementation of a High-Efficiency T-Type Three-Level Inverter for Interior Permanent Magnet Synchronous Motor Drive Systems

Abstract

This study presents a high-efficiency T-type three-level inverter for interior permanent magnet synchronous motor (IPMSM) drive applications, featuring a comprehensive performance comparison with a conventional two-level inverter. To address the high switching losses and noticeable harmonic distortion typically associated with conventional two-level configurations, the T-type architecture is developed and evaluated. First, PLECS simulations are conducted to verify the proposed dual-loop control architecture, which integrates field-oriented control (FOC), space-vector pulse-width modulation (SVPWM), and a neutral-point voltage balancing mechanism. Subsequently, a 2.2 kW experimental platform is constructed using silicon carbide (SiC) wide-bandgap (WBG) semiconductor devices. To characterize the dynamic switching behavior of the adopted SiC MOSFETs, a dedicated double-pulse test (DPT) platform is developed to evaluate their switching losses and determine appropriate gate-drive parameters. In addition, the digital control firmware is implemented on a digital signal processor (DSP) platform. The dual-loop control algorithms, SVPWM strategy, and two-layer protection framework are implemented as real-time executable routines, enabling close integration of the control software and hardware platform. Finally, motor drive experiments at switching frequencies of 20 kHz and 40 kHz are performed to validate the proposed system. The experimental results demonstrate that the developed architecture significantly reduces phase-current total harmonic distortion (THD) and improves overall energy conversion efficiency compared with a conventional two-level inverter, confirming its potential for high-efficiency next-generation electric vehicle applications.