Accuracy-Aware Approximate Laplacian Filter for Energy-Efficient Processing

Abstract

This work presents energy-efficient ASIC implementations of Laplacian filters using approximate computing techniques. Two architectures, standard and isotropic Laplacian filters, are developed with optimized adder-tree structures and shift-based multiplications. To improve hardware efficiency, 19 state-of-the-art approximate adders are integrated and evaluated at multiple approximation levels. All designs are synthesized under identical conditions in 65 nm CMOS technology and assessed with the FALSAx framework, enabling rigorous joint analysis of hardware metrics and output quality. Experimental results show that the proposed architectures achieve up to 40% reductions in energy and area with negligible accuracy loss, while more aggressive configurations yield over 70% energy savings. Additionally, approximate designs significantly improve the maximum operating frequency, achieving speedups of up to 110%. These results confirm the suitability of Laplacian filters for approximate computing, enabling substantial efficiency gains while preserving visual quality fidelity.