A Reconfigurable Transprecision SIMD-MAC PE for Mixed-Precision Edge-AI Applications

Abstract

Edge-AI systems require arithmetic hardware that can support multiple numerical precisions under strict power and resource constraints. This work presents a reconfigurable transprecision SIMD multiply-accumulate (MAC) architecture supporting 1 ×BF16, 2 ×FP8, 4 ×FP4, and 2 ×INT4 operations within a unified framework for low-power AI inference. To improve hardware efficiency, a reusable exact 4 × 4 multiplier is used across all precision modes. For BF16 operation, approximate mantissa multiplication is carried out by computing dominant and cross partial products while excluding the least-significant partial product to reduce arithmetic complexity. The proposed six-stage pipelined architecture improves hardware utilization and supports scalable mixed-precision execution. Compared with recent approximate multiplier designs, the proposed multiplier reduces LUT utilization and power-delay product (PDP) by 32.5% and 32.3%, respectively. FPGA implementation on VC707 achieves 220 MHz operation with lower hardware utilization and power consumption. Implemented in 28 nm technology, the proposed ASIC design operates at 1.530 GHz with an area of $0.0065 ~\text{mm}^{2}$, corresponding to up to 50.0% lower area than recent reconfigurable MAC architectures. These results show a good balance among performance, silicon efficiency, and energy consumption for resource-constrained edge-AI accelerators.