A Hybrid OR-MUX Lower-Part Approximate Adder for Energy-Efficient Edge AI Inference on FPGA

Abstract

Approximate computing has become a prominent design paradigm for energy-constrained edge AI hardware, where relaxed arithmetic precision enables significant gains in speed, area, and power. This paper presents a novel $n$-bit Hybrid OR-MUX Lower-Part Approximate Adder (HOMAxA-1) that divides operands into an approximate lower part (bits $[k-1: 0]$) and an exact upper part (bits $[n-1: k]$). In the 8-bit instance $(n=8, k=4)$, the lower nibble employs bitwise OR with generate-based compensation for sum bits [1:0], governed by OR for bit [2], and MUX-controlled carry-select for bit [3]; the upper nibble part computes an exact addition using an AND-generated carry. Exhaustive evaluation over all 65,536 input combinations under a carry-preserving 9-bit output convention yields ER=57.81%, MED=1.5625, NMED=0.00306, and WCE=7. Benchmarked against five conventional, well-established approximate adders, HOMAxA-1 attains the lowest NMED and lowest WCE of the compared set. The proposed architecture was implemented using synthesizable Verilog HDL and validated on a Xilinx Artix-7 FPGA using the Xilinx Vivado.