Self-Adaptive Neural Calibration of Dynamic Comparators Using Time-Domain Encoding

Abstract

This work presents a dynamic comparator calibration architecture that works entirely in the digital domain with no analog correction element of any kind. The system is built around a StrongARM latch comparator paired with a 7-bit on-chip timeto-digital converter (TDC). Since comparator offset shifts the switching instant by an amount proportional to $V_{\text{os}}$, the TDC output q[6:0] carries a complete encoding of the offset at every clock cycle. A two-layer neural network learns the inverse of this mapping and recovers the true input voltage from the timing measurement: the hidden layer is trained offline and stored as fixed w eights, w hile t he o utput l ayer a dapts o n-chip d uring a short calibration phase. Training uses an on-chip ramp as the only reference, so no external instrument or reference converter is needed at any point. After training converges, the network applies the correction at full clock speed using frozen weights, and a digital comparator produces the corrected output decision. Implemented in 180 nm CMOS at 1.8 V and 1 GHz, Monte Carlo results with $N=250$ runs at the TT corner show mean offset reduces from 36 mV $(\sigma=0.9 \text{mV})$ before calibration to $5 \text{mV}(\sigma=0.09 \text{mV})$ after, which is an improvement of around 86%. Across all PVT corners the residual stays within acceptable bounds. The neural calibration block fits u nder $60 \mu \mathrm{m}^{2}$ and draws less than $5 \mu \mathrm{W}$ during normal operation.