Scalable Fault-Tolerant Memory Architectures with ECC and on-Demand Redundancy

Abstract

This work assesses three fault-tolerant memory architectures with increasing redundancy levels for radiationhardened systems. The baseline architecture (S0) uses a single ECC-protected memory bank. The S1 architecture introduces dual modular redundancy combined with cross-bank syndrome comparison, which eliminates Silent Data Corruption (SDC) through independent syndrome verification. A heterogeneous configuration (S1-HET) further improves fault coverage by applying a heterogeneous ECC scheme. The S2 architecture adopts a Lazy-TMR strategy that reads only two banks in the common case and activates the third bank for majority voting only when inconsistencies are detected. Simulation results under adjacent, burst, and distributed error patterns show that S0 correction capability drops below 40% when error patterns exceed the ECC design limits. In contrast, S1 eliminates SDC with a $2 \times$ area overhead while maintaining correction rates above 95% for up to five distributed errors. The S2 architecture achieves the highest robustness, sustaining 97% correction under 8-bit burst errors and 100% up to six distributed errors. At the same time, a Fast Path mechanism limits the effective latency to two bank reads in the common case.