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CHIMERA: A Chaotic Hopfield–Integrated Memristive Entropy Architecture for FPGA PRNGs

Aug 2026 · International Symposium on VLSI Design and Test · pp. 466-471 · 0 citations · 13 references

Abstract

This paper presents CHIMERA, an FPGA-efficient chaotic pseudo-random number generator (PRNG) family built around a four-neuron memristive Hopfield neural network (MHNN) integrated by a pipelined fourth-order Runge-Kutta (RK4) solver. Two complementary design points are developed on a Xilinx Artix-7 XC7A100T: (i) CHIMERA-S, a compact singlesource core in signed Q6.58 fixed-point with a nested outer/inner FSM that serialises the 23-step derivative pipeline onto a shared 128-bit truncated multiplier, augmented by a 64-bit LFSR for seed perturbation and noise injection and a hardware Von Neumann debiaser; and (ii) chimera-h, a dual-source hybrid in Q24.40 with a parallel derivative datapath, 130-bit truncated multiplications, and XOR-fused entropy from a Q24.63 Bernoulli map $(B=1.75)$. A bit-accurate Python reference provides the golden bitstream. NIST SP 800-22 evaluation across 188 sub-tests at $\alpha=0.01$ on 100 streams of 1 Mbit confirms that all variants satisfy every criterion. chimera-h attains the highest mean pass proportion (0.9928) and exceeds the MHNN-only variant in 108 of 188 tests; it closes timing at $\mathbf{1 0 0 M H z}$ with +1.238 ns slack, draws 0.312 W, and reaches an estimated $\approx \mathbf{3 3 8}$ Mbit/s. chimeras closes at $\mathbf{2 5}$ MHz with + 0.282 ns slack, draws 0.337 W, and fits in 66% LUTs / 88% DSPs. Together the two points characterise an area-throughput-quality tradeoff curve for MHNN-based PRNGs on mid-range FPGAs.

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