MemMax: Memory-Parallel FPGA Optimization for Bandwidth-Bound IoT Image Processing
Abstract
Memory-bound workloads increasingly dominate modern data-intensive systems, especially in Internet of Things (IoT) pipelines where large volumes of sensor and image data must be processed under strict latency and power constraints, yet CPUs quickly saturate their memory bandwidth even with many cores. FPGAs offer higher sustained bandwidth through customizable datapaths, but naively porting CPU-style C code to high-level synthesis (HLS) often produces severely underutilized hardware. This paper examines how to restructure Cstyle oneAPI SYCL code to unlock FPGA performance using a representative bandwidth-bound task: horizontally flipping PNG images. Starting from a naive HLS design that performs up to 1,480× slower than a Xeon Platinum 8360 CPU, we apply FPGA-centric optimizations including producer-consumer dataflow pipelines, multi-channel DDR parallelism, burst-aligned memory access, and loop unrolling. The optimized design scales to 16 kernels across four DDR channels and outperforms a 40core CPU by nearly 25% on million-image workloads. Our results show that effective memory-bound optimization is essential for achieving competitive FPGA performance and provide practical guidelines for HLS-based FPGA acceleration in data-intensive domains.