TL;DR
The proposed Double MAC unit with dynamic precision scaling has showed twofold improvement in throughput and 15% improvement in power consumption, and proves advantageous in convolution layers, where greater precision is required for final classification and smaller precision in initial stage.
The widespread deployment of deep neural networks on edge devices faces a severe imbalance between computational demand and available power, while devices frequently switch between low-power standby and highperformance detection modes. Existing general-purpose processors, graphics processing units, and fixed-precision...
The increasing adoption of modern embedded platforms, edge devices, and AI driven systems has led to higher computational demands. To facilitate that, there should be hardware acceleration techniques capable of delivering higher throughput with minimal latency. Most of the traditional hardware accelerator architectures...
This paper presents the design, simulation, and ASIC-focused implementation of a Binary Convolutional Neural Network (BCNN) tailored for energy-efficient edge AI applications. The proposed architecture utilizes binarized weights and activations, substituting standard multipliers with XNOR-popcount operations to reduce...
The growing demand for portable and high-performance computing systems has intensified the need for low-power VLSI designs. Among various digital signal processing (DSP) components, the Multiplier Accumulator (MAC) unit plays a crucial role in applications such as filtering, convolution, and image processing. However,...
Deep Neural Networks (DNNs) are critical to modern AI applications, yet their deployment on standard CPUs and GPUs is constrained by high power consumption and computational latency, particularly in resource-constrained edge environments. To address these limitations, this paper presents the design and implementation o...
CNN inference on edge hardware is constrained by memory bandwidth, redundant logic, and the area overhead of fully parallel multiply-accumulate (MAC) units. This paper presents a hardware-efficient CNN accelerator with an SRAM-based architecture optimised for classifying 28×28 grayscale images. Input images are ingeste...
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