It is experimentally demonstrated that the 1D CNN architecture under low signal-to-noise ratio conditions exhibits higher classification accuracy compared to classical methods and approaches the theoretical optimum.
Abstract
The article addresses the problem of a tonal signal binary detection in the presence of additive white Gaussian noise in real-time. A comparative analysis of classical methods (energy detector, quadrature matched filter) and neural network approaches (1D Convolutional Neural Network – 1D CNN, Multilayer Perceptron – MLP) is conducted during their hardware implementation on the STM32F407 microcontroller and the Artix-7 Field-Programmable Gate Array (FPGA). It is experimentally demonstrated that the 1D CNN architecture under low signal-to-noise ratio (SNR from –10 to –8 dB) conditions exhibits higher classification accuracy compared to classical methods and approaches the theoretical optimum. The impact of post-training 8-bit quantization on model size and accuracy is investigated. Practical hardware implementation metrics are provided: for the STM32 platform, the inference time is 2.1 ms with an average current consumption of 7 mA, while the FPGA implementation ensures a processing latency of less than 1 μs with absolute determinism. Practical recommendations for selecting a hardware platform based on power consumption, latency, and system flexibility requirements are formulated.
A combined hardware-andalgorithm design that pairs a carefully regularized binarized neural network (BNN) with a compact, variable-precision FPGA processor to enable accurate, real-time object detection without relying on off-chip memory is proposed.
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A comparative analysis of dynamic stochastic computing using a convolutional neural network for MNIST digit classification indicates that dynamic stochastic computing can serve as an efficient alternative for the design and implementation of neural-network accelerators.
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