AI Networking Cookbook: Practical recipes for AI-assisted network automation and development
TL;DR
This paper presents an FPGA implementation of the ASCON-128 lightweight cipher employing a pipelined finite-state-machine design alongside a highly optimized sequential design and proposes a cost-effective, high-performance hardware architecture designed to mitigate power analysis attacks.
A lightweight cryptographic hardware is crucial in cases where computing capabilities, silicon area and power requirement are limited. In this paper, the design of FPGA-based FPLP architecture for Trivium stream cipher algorithm is provided with analysis of the hardware parameters of FPLP architecture in Spartan-7, Art...
Elliptic curve cryptography (ECC) combines strong security with short keys, which makes it a good fit for embedded and IoT devices. In these systems, scalar point multiplication is usually the most demanding operation. Published hardware results are hard to compare because researchers work with different platforms, ope...
The growing deployment of Internet of Things (IoT) devices, embedded systems, and hardware security platforms has increased the demand for lightweight cryptographic architectures capable of delivering strong security under stringent area and power constraints. Although the Advanced Encryption Standard (AES) is widely a...
With the increasing demand for energy-efficient edge computing, maintaining secure data processing without sacrificing performance has become a critical requirement. The proposed system introduces a flexible cryptographic engine implemented on the Zynq-7000 FPGA, capable of supporting multiple hashing algorithms, inclu...
Cryptographic hash functions over integers modulo a prime play a decisive role in the efficiency and security of proof systems for computational integrity. Early designs focused on compact arithmetic circuits and efficient software execution, primarily targeting general-purpose CPUs rather than hardware accelerators. T...
PipSORE is introduced, a novel architectural optimization focused on area and power and the single- and multi-core PipSORE architectures are proposed and evaluated and utilize the outer-round pipelining technique.
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