Jul 2026· Annual International Computer Software and Applications Conference· pp. 1959-1966· 0 citations· 20 references
Computer Science
Abstract
The paper introduces a comprehensive framework for parallel runtime verification designed to monitor concurrent systems that utilise shared-variable communication mechanisms operating under interleaved concurrency model. The proposed framework validates system behaviour during execution to confirm adherence to correctness specifications or identify violations thereof. Concurrent systems necessitate distinct correctness criteria compared to sequential programs, particularly regarding deadlock avoidance and mutual exclusion protocols when multiple processes access shared resources under interleaved concurrency models. Traditional sequential verification frameworks lack the architectural capability to monitor parallel systems effectively, as they are fundamentally designed to track single processes rather than multiple concurrent processes executing simultaneously. This work addresses various challenges in ensuring correctness of parallel programs at both hardware and software layers while providing a theoretical analysis comparing verification methodologies including theorem proving, model checking, testing, and runtime verification. The framework uses Interval Temporal Logic (ITL) as its formal foundation alongside its expressive power for specifying complex temporal properties of parallel systems. A detailed exposition of the framework's core components, their operational roles, and their integration within the overall verification architecture is presented, demonstrating the practical applicability of runtime verification techniques for ensuring correctness in parallel computing environments.
The permissioned state machine (PSM) approach, which extends TLA-style protocol reasoning with ideas from concurrent separation logic, enables the developer to specify and verify complex protocols, such as Tulip, by breaking them down into smaller modules.
Yun-Sheng Chang, Joseph Tassarotti, Frans Kaashoek et al.· Proceedings of the ACM SIGOP...· 0 citations
Interrupt-driven programs are extensively utilized in embedded systems for safety-critical domains. However, uncertain interleaving executions of enabled tasks with different priorities often lead to concurrency defects. In this context, assertion violation detection is a fundamental method to ensure program correctnes...
Bin Yu, Xu Lu, Yuanzhe Liu et al.· ACM Transactions on Embedded...· 0 citations
DeterV is a deterministic parallel runtime which uses Verus to verify its correctness and equivalence to serial execution in the input order and attains a 3:1 proof-to-code ratio and incurs only trivial runtime overhead compared to an unverified baseline.
Zheng-Qing Liu, Marios Kogias· Proceedings of the 14th Work...· 0 citations
This work presents a technique for compiling the synchronous fragment of STL (SSTL) into synchronous observers in the dataflow language Lustre, and contributes an interactive visualiser that renders a property's three-valued verdict over an editable trace.
Logan Kenwright, Partha S. Roop, Sobhan Chatterjee et al.· 0 citations
This study proposes a rigorous formal verification methodology based on a triple-constraint framework to prove system reliability prior to the implementation phase, and firmly establishes the proposed methodology as a highly robust and practically viable solution for evaluating complex, resource-contended clinical work...
Acep Taryana, D. Adzkiya, Muhammad Syifa'ul Mufid et al.· Computers, Materials & C...· 0 citations
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