A Sail-guided FP-RVVTS flow that uses Sail RISC-V as an executable RISC-V specification for differential verification of RISC-V Floating-Point (FP) implementations, from Instruction Set Simulator s to Register Transfer Level (RTL) designs.
Janus is presented, an LLM-assisted framework that synthe-sizes custom instructions integrated into the Ibex RISC-V core while keeping correctness outside the agent, demonstrating a practical path for using LLMs to explore ISA specialization without making the agent part of the trusted correctness boundary.
A UVM 1.2 environment and methodology that wraps a bus-master SIMT DUT with role-inverted agents, integrates Vortex's functional simulator (SimX) as a per-configuration golden model over DPI-C, and renders verdicts via two injection-qualified checkers.
This work presents a comprehensive analysis of contemporary hardware fuzzing techniques applied across three major abstraction layers: Instruction Set Architecture (ISA), microarchitecture, and Register-Transfer Level (RTL). Our study examines key factors including input stimulus quality, mutation strategies, feedback...
LACE is presented, an LLM-aided multi-agent workflow that translates natural-language ISAX intents into a compact two-level IR, performs retrieval-guided localized RTL edits over large repositories, and closes the loop with a compiler-agnostic riscv-formal checking flow.
This study proposes a supervised learning framework that predicts MBIST area and test time directly from RTL-level design parameters without synthesis, which enables faster estimation of MBIST costs and supports more efficient design decisions in memory IP development.
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