Design of Secure Hardware Architectures for Post-Quantum Cryptography Applications

Abstract

A cryptographically relevant quantum computer is no longer science fiction, and that reality has forced the standardization of post-quantum cryptographic (PQC) algorithms: the lattice-based Kyber (ML-KEM) and Dilithium (ML-DSA), the code-based Classic McEliece, and the hash-based SPHINCS+ among them. Getting these algorithms running on embedded systems, IoT nodes and hardware security modules (HSMs) requires more than porting software Post-quantum cryptography needs hardware that does it all. It needs to be fast, compact and energy-efficient, while also being a fortress against physical hacking tactics like side-channel or fault-injection attacks. To solve this problem we built a secure hardware accelerator for PQC from scratch. Its heart is a highly protected Datapath with a masked polynomial arithmetic unit, constant-time engines for both NTT and noise sampling, a Keccak/SHA-3 core, and dedicated blocks fully dedicated to hiding data and fault detection. We thoroughly validated this architecture with FPGA simulations for five top NIST-backed PQC algorithms. The standout result? Our first-order masking effectively neutralizes 96% of sidechannel data leaks compared to a standard, unprotected core. The trade-offs are well worth the security gain, requiring just a 38% increase in chip footprint and a 22% bump in processing time. Push to fourth order (d=4) and leakage reduction exceeds four orders of magnitude, with overhead scaling accordingly. Throughput, resource utilization, and power trade-offs are quantified across all five schemes, along with practical guidance for picking a masking order and hiding strategy to match a given threat model and resource budget.