Jul 2026· IEEE International Symposium on High-Performance Parallel Distributed Computing· pp. 592-593· 0 citations· 2 references
Computer Science
TL;DR
DPIO is presented, a unified I/O processing stack designed to harmonize the collaboration between CPU and DPU in NVMeoF environments, achieving near-optimal system performance across diverse workloads.
Abstract
To alleviate the overhead of moving massive data in modern data centers, Data Processing Units (DPUs) are increasingly deployed to offload NVMe-over-Fabrics (NVMeoF) remote storage access from the CPU. However, current heterogeneous CPU-DPU systems suffer from inflexible resource partitioning, leading to suboptimal utilization of computational power and network bandwidth. In this paper, we present DPIO, a unified I/O processing stack designed to harmonize the collaboration between CPU and DPU in NVMeoF environments. By implementing fine-grained task orchestration, DPIO effectively bridges the performance gap between DPU offloading and CPU processing, achieving near-optimal system performance across diverse workloads. Our real-world implementation demonstrates that DPIO delivers over 2 × higher throughput compared to conventional DPU-centric NVMeoF approaches, significantly enhancing the efficiency of data-intensive applications.
Spillway introduces a DPU-host hybrid data plane that repurposes idle host CPU resources to process spillover traffic when the DPU becomes the bottleneck, and decouples virtual switching capacity from static DPU hardware limits.
Xiaochong Jiang, Dian Fan, Yilong Lv et al.· Conference on Applications,...· 0 citations
ParaFlowO is proposed, an architecture that Parallelizes processing elephant Flows across multiple CPU cores while preserving in-Order delivery and integrates a lightweight reordering mechanism to preserve packet order and controls parallelism to mitigate contention on shared state.
Chang-Gang Zheng, Bowen Yang, Jin Ke et al.· Asia-Pacific Workshop on Net...· 1 citation
Hierarchical Data Storage Systems (HSSs) provide a cost-effective architecture that balances capacity and performance through internal data migration. Prior work has primarily focused on optimizing individual migration tasks, either within or across HSS tiers, or on exploiting device bandwidth to improve overall throughput. These approaches treat migration tasks in isolation, and the performance implications of executing heterogeneous migration tasks concurrently remain largely unexplored despite their prevalence in real-world HSS deployments. The growing adoption of Direct Data Access (DDA) architectures, in which accelerators access storage without CPU mediation, further amplifies this problem by removing a natural bandwidth arbiter from the I/O path.
This paper presents an in-depth analysis of data migration behavior in commercial HSSs, uncovering substantial performance variability when multiple migration tasks execute concurrently. To mitigate this issue, we propose PASCAL, a system-level bandwidth orchestration framework that improves performance robustness in production-grade HSSs. Inspired by hydraulic systems, PASCAL adapts pressure/backpressure-style coordination to the multi-task migration setting: it treats each tier as a pressurized vessel and uses pressure gradients to allocate bandwidth across cache flush, tiering, garbage collection, and DDA flows. We evaluate PASCAL on a commercial OceanStor HSS across three hardware configurations and eight workloads spanning database, AI training, AI inference, and production traces. PASCAL achieves up to 20% higher throughput, 67% lower tail latency, and 79% reduced throughput jitter compared to local state-of-the-art controllers, while also stabilizing the performance jitter introduced by DDA architectures.
Ji Zhang, Li Liu, André Brinkmann et al.· Proceedings of the VLDB Endo...· 0 citations
Modern HPC systems increasingly rely on tiered storage architectures with SSDs serving as a critical performance tier. However, the inherent asynchronous I/O characteristics of SSDs, including read/write bandwidth asymmetry and interference, pose significant challenges for traditional I/O schedulers. These challenges are exacerbated by the convergence of bursty HPC write workloads (e.g., checkpointing) and sustained AI read workloads (e.g., data streaming) on shared SSD infrastructure. Existing schedulers fail to adequately address these combined workloads, leading to suboptimal resource utilization. This paper introduces HARMONI, a heterogeneity-aware reinforcement learning scheduler for mixed I/O in HPC storage systems. HARMONI leverages a graph neural network (GNN) to encode task-SSD dependencies and a hybrid interference predictor to adapt to hardware and I/O variations. Experimental results across diverse HPC and AI workloads demonstrate that HARMONI significantly reduces average makespan by up to 90% compared to state-of-the-art schedulers, effectively bridging the gap between evolving storage hardware and the dynamic I/O demands of modern HPC systems.
Ze-Xi Cai, Tong Zhao, Shadi Ibrahim et al.· ACM Transactions on Architec...· 0 citations
Erasure coding provides efficient fault tolerance for large-scale distributed storage systems. However, its data repair process is well-known to be resource-intensive. We find that conventional host-centric, TCP-based repair architectures suffer from severe resource contention. Even in high-bandwidth networks, such interference slows repair operations and degrades service quality. To address this limitation, we propose DPUEC, a novel architecture that fully offloads the entire repair process to a Data Processing Unit (DPU). DPUEC leverages Remote Direct Memory Access (RDMA) to enable kernel-bypass data transfers and utilizes the onboard multi-core processors of DPU for highly parallel decoding. This design establishes a physically isolated data plane for repair traffic, completely bypassing host resources. Our prototype evaluation shows that DPUEC improves repair throughput by 133% - 181% over the state-of-the-art approach across different workloads. More importantly, DPUEC delivers true performance isolation. It eliminates any interference with foreground applications and reduces host CPU utilization on the recovery node to nearly zero.
The AI hardware boom has driven modern data centers toward HPC-style architectures centered on GPU clusters, RDMA-capable networks, and high-throughput NVMe storage. While designed primarily for training and inference, this infrastructure also creates new opportunities for designing the next generation of scalable database systems for analytical workloads on top of such data centers. In particular, the combination of GPU-centric computation, fast networking, and fast storage enables disaggregated architectures that extend beyond single-node, GPU-memory-resident execution.
This paper discusses the challenges and design considerations of analytical query processing on such disaggregated GPU-centric systems. We examine how modern networks and storage enable distributed execution and out-of-memory processing, and how their interaction shapes end-to-end performance. Our recent results show that naïve use of existing I/O abstractions can underutilize both compute and I/O bandwidth due to insufficient overlap between computation and data movement. We therefore identify effective I/O-computation overlap as a key requirement for fully exploiting the AI data center stack, and outline future research directions for next-generation analytical database architectures.
Ji-Gao Luo, Nils Boeschen, Muhammad El-Hindi et al.· Datenbank-Spektrum· 0 citations
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