NTV-CIM: System-Level Assessment of Near-Threshold Digital Compute-in-Memory Accelerators

Abstract

To deal with the growing needs of deep neural networks (DNNs), energy efficiency techniques such as near-threshold voltage (NTV) have been deployed, promising to reduce energy consumption by decreasing the supply voltage of accelerators. Despite its potential, the systematic application of NTV in digital compute-in-memory (DCIM) and the interplay between voltage scaling, performance, power, and reliability at the DNN level remain underexplored. In this work, we propose a system-level design framework for modeling, mapping, and architectural exploration of DCIM accelerators operating under NTV. We model and explore the configuration space of multivoltage-island DCIMs and integrate hardware (HW)-awareness that accounts for process variation (PV) and device-level reliability to avoid errors during computation. We evaluate in comparison to synthesized DCIMs in 22 nm, targeting CNNs and a Vision Transformer. Our results show up to $\times 3.35$ reduction in energy consumption of NTV DCIMs against equivalent standard compute-in-memory (CIM).