CIM-Blocks: A Synthesizable Multi-Precision Compute-in-Memory CGRA with Bit-Serial Data Reuse

Abstract

Neural networks (NN) for edge AI require efficient execution to balance performance, power, and flexibility. Since NN models evolve rapidly and exhibit different quantization sensitivities, accelerator architectures must support multiple precisions and convolution structures while maintaining energy efficiency. Coarse-Grained Reconfigurable Architectures (CGRAs) provide flexibility through interconnected processing elements and reconfigurable data paths, but data transfers between compute units and local memories introduce significant energy overhead. Compute-in-Memory (CIM) architectures reduce this overhead by performing computations close to memory and minimizing data movement. This work proposes CIM-Blocks, a synthesizable CIM-based CGRA architecture that integrates standard-cell-based CIM functionality directly into the reconfigurable fabric. CIM-Blocks supports flexible 4bit, 8-bit, 12-bit, and 16-bit weight execution through a reconfigurable adder tree and interconnected small CIM FUs. Implemented in GF 22nm technology, CIM-Blocks reduces switchbox data movement power by 44% and achieves nearly 3× higher energy efficiency than a reference CGRA architecture, reaching 307 GOPS/W. The architecture is inherently scalable through modular CIM blocks and a reconfigurable interconnect, enabling these benefits to extend to larger CGRA arrays and more demanding AI workloads.