Surrogate-assisted DTCO for 1T1C FeMFET Bitcells: A Comparative Study on Model Choice and Data Sampling

Abstract

Design–Technology Co-Optimization (DTCO) of emerging memory technologies requires efficient exploration of large and highly nonlinear design spaces, making exhaustive simulation computationally expensive. Surrogate modeling provides an attractive alternative by learning the mapping between design parameters and circuit-level metrics from a limited set of simulations. However, the impact of the modeling paradigm and training dataset generation strategy remains under-explored, particularly for multi-input multi-output problems with heterogeneous target scales. In this work, we evaluate three machine learning surrogate approaches: Multi-Layer Perceptron (MLP), Gaussian Process Regression (GPR), and Random Forest (RF) for bitcell-level modeling of a 1T1C FeMFET. We compare datasets generated using Design of Experiments (DoE) and genetic algorithms and assess model accuracy, scalability with training size, and suitability for surrogate-assisted multi-objective optimization. The resulting Pareto fronts define the feasible trade-off space at the bitcell level, which serves as the input design space for subsequent array-level exploration in crossbar architectures for in-memory computing.