DESIGN AND EVALUATION OF FINFET-BASED APPROXIMATE MODIFIED BOOTH MULTIPLIER FOR ENERGY-EFFICIENT VLSI SYSTEMS

Abstract

In the progress of energy-efficient digital multiplication systems, approximate multipliers have been proven to be a good solution to attain high energy efficiency with acceptable computational precision. This paper proposes a 22 nm FinFET-based approximate Modified Radix-8 Booth multiplier which is based on Modified Radix-8 Booth recoding, selective partial-product approximation, controlled truncation, and an optimized reduction and accumulation network to minimize arithmetic complexity and switching activity. This architecture was modeled in VHDL and designed using an ASIC design flow using a 22 nm standard-cell library. Post-layout evaluation showed about 63.4% silicon area reduction, 55.1% propagation delay reduction, and 65.6% power consumption reduction when compared with an exact Booth multiplier with lower Power–Delay Product (PDP) and Area–Power Product (APP). The application-level validation with representative image processing operations resulted in a PSNR of 41.2 dB and SSIM of 0.995, which validated the proposed approximation strategy to maintain high computational quality. The proposed multiplier is well suited for low-power digital signal processing, multimedia processing, and embedded VLSI systems as it gives an effective trade-off between implementation efficiency and arithmetic accuracy.