Research on electrical performance enhancement of carbon nanotube MOSFETs based on thermal annealing optimization

Abstract

Carbon nanotube thin-film transistors (CNT-TFTs), owing to their exceptional carrier transport properties and stable quasi-one-dimensional structure, are widely recognized as ideal candidates for next-generation nano-electronic devices. However, the practical performance of CNT-based devices is often limited by the interference of metallic impurities, the high contact resistance at the metal-nanotube interface, and the presence of charge trap states and residues at the interface between the CNT channel and the SiO2 gate dielectric. These factors not only reduce carrier mobility but also induce severe hysteresis effects. In this work, back-gate p-type Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) were fabricated using solution-deposited CNT channels and thermally evaporated Au source/drain electrodes. A post-annealing process in an argon atmosphere (200 °C, 30 min) was introduced as a critical post-treatment step. Experimental results demonstrate that the annealing effectively purifies the channel interface and improves the carrier transport mechanism. Comparative analysis reveals that after annealing, the on/off current ratio of the devices is enhanced by nearly an order of magnitude, the off-state current is on the order of 10−12 A, and the subthreshold swing (SS) is significantly reduced. The annealing treatment markedly improves the switching characteristics of the devices, providing an effective process reference for the fabrication of high-performance CNT-based electronic devices.