Ultra lightweight AES S-box ASIC hardware for low-power IoT devices

Abstract

In pursuit of secure, resource-constrained cryptographic hardware for the Internet of Things (IoT), this work presents an Advanced Encryption Standard (AES) Substitution-box (S-box) architecture optimized for ultra-low power, minimal area, and high throughput. The proposed design leverages composite Galois Field (CGF) arithmetic over \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\textrm{GF}(((2^4)^2))$$\end{document}, incorporating isomorphic and inverse-isomorphic transformations to reduce inversion complexity in \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\textrm{GF}(2^8)$$\end{document}. A unified transformation engine merges affine and inverse-isomorphic operations, significantly minimizing logic redundancy. The architecture is based on purely combinational logic, thereby eliminating the need for sequential control and enabling single-propagation-cycle substitution. Post-layout static timing analysis indicates that the design achieves a maximum operating frequency of 892.86 MHz, which equates to a throughput of 7.14 Gbps. Logic minimization, substructure reuse, and shared multiplier-XOR networks are applied to optimize gate-level complexity and energy consumption further. Physical design implementation and validation were conducted using the Synopsys digital design flow with a \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$32~\textrm{nm}$$\end{document} CMOS standard cell library, achieving a compact core area of \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$411~\mathrm {\mu m}^2$$\end{document} and total power of just \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$192~\mathrm {\mu W}$$\end{document}. The resulting hardware efficiency reaches 17.39 Mbps/\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\mu$$\end{document}m\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$^{2}$$\end{document}, indicating improved area-to-throughput efficiency under comparable implementation conditions. This design demonstrates that advanced algebraic decomposition, linear transformation fusion, and combinational datapath modeling can effectively address the growing demand for lightweight, fabrication-ready cryptographic primitives. The architecture serves as a hardware-efficient implementation suitable for deployment in secure IoT edge devices, smart sensors, and energy-constrained embedded systems.