A Sparsity-Aware Spiking Neural Network Accelerator for Real-Time Gesture Recognition on Microcontroller-Class Edge Devices

Abstract

Spiking Neural Networks (SNNs) are highly touted as energy-efficient alternatives to traditional deep networks, because they process information in a sparse manner and rely on events. However, the vast majority of published accelerator work in SNN targets FPGA fabrics or dedicated neuromorphic chips – not the low-cost microcontroller (MCU) class hardware used for most deployments in the real world of wearables and IoT devices – and the value of SNN in such settings is therefore not well understood from an empirical perspective. In this paper, we address this need by proposing a sparsity-aware SNN pipeline for real-time gesture recognition specifically targeted to compute and memory constraints of microcontroller class. The proposed method is implemented on the UCI Human Activity Recognition (HAR) dataset, with a compact Leaky-Integrate-and-Fire network trained using surrogate-gradient descent and a datasheet-grounded cost model based on a Cortex-M4F level MCU. When compared with a parameter-matched CNN baseline, the SNN shows a test accuracy of 48.34% ± 2.21% and an estimated 95.5% fewer MAC operations and around 22× lower estimated energy and latency across the five random seeds. The design choices are supported by a systematic ablation study and the light weight backpropagation-free personalization mechanism allows the system to learn a new gesture from a single demonstration. The results place sparsity-aware SNN accelerators on par as a promising and energy-efficient approach to edge devices with microcontroller capabilities.