NeuSym-HLS: Efficient Hardware Acceleration of Deep Neural Networks With Symbolic Distillation and High-Level Synthesis

Abstract

The domain-specific hardware accelerators for deep neural network (DNN) inference have been widely adopted, particularly in resource-constrained edge computing scenarios but face a fundamental tradeoff among accuracy, on-chip resource utilization, and inference latency. Traditional compression techniques, such as pruning and quantization, help alleviate this tradeoff but can fall short when aggressive hardware efficiency is required. We present NeuSym-high-level synthesis (HLS), a partial symbolic distillation, and HLS flow for compressing and accelerating DNN inference at the edge. NeuSym-HLS replaces the selected layers of a trained DNN with compact analytic expressions obtained through symbolic regression (SR) and implements the resulting hybrid DNN–symbolic model as an efficient hardware accelerator. We evaluate NeuSym-HLS on two computer-vision workloads with field-programmable gate array (FPGAs): a multilayer perceptron (MLP) for MNIST and a binary-classification MLP for SVHN. On MNIST, NeuSym-HLS achieves a $2.6\times $ inference speedup while reducing LUTs by 47%, DSPs by 47%, and BRAMs by 55%, with negligible accuracy decrease from 97.50% to 95.27%.