More Secure Compound Logic Locking Techniques with Security Assessment via Removal and Structural Analysis Attacks

Abstract

Logic locking is a widely used hardware security technique that protects digital circuits by inserting secret key inputs so that correct functionality is achieved only when the valid key is applied. When an incorrect key is used, the circuit produces incorrect outputs, preventing the circuit from operating as intended. However, several traditional locking techniques remain vulnerable to automated key recovery attacks such as satisfiability (SAT) based attacks. To address this challenge, Compound Logic Locking (CLL) techniques that combine multiple locking mechanisms are explored to improve circuit protection. In this paper, different compound locking approaches, including Random Logic Locking combined with Anti-SAT (RLL + AntiSAT), Input Dependent Key Logic Locking combined with Anti-SAT (IDKLL + AntiSAT), and Modified IDKLL + AntiSAT are implemented and analyzed. In addition, a unique key-based IDKLL architecture using NAND gate reconstruction is proposed to enhance security while maintaining efficient hardware implementation. All designs are modeled using Verilog HDL and evaluated through simulation and synthesis to analyze hardware parameters such as area, power, and delay. The security strength of the locked circuits is further examined using oracle-less and oracle-guided SAT attack models. Experimental observations show that the proposed input-dependent locking structures increase resistance to key recovery while maintaining acceptable hardware overhead.