This work compares two recent multicore neuromorphic systems implemented in the same 22-nm FDSOI technology and explicitly optimized for inter-core event communication, and discusses routing-aware training as a means of jointly optimizing neural connectivity, task performance, and hardware mappability.
Abstract
As neuromorphic systems scale beyond a single core, inter-core event communication can become a dominant contributor to memory footprint, latency, and energy consumption. Biological neural systems address a similar scaling challenge through small-world organization, combining dense local connectivity with sparse long-range projections. In this work, we compare two recent multicore neuromorphic systems implemented in the same 22-nm FDSOI technology and explicitly optimized for such connectivity. The first, NeoCorAl, uses an asynchronous packet-switched tree with hierarchical multicast, whereas the second, MOSAIC, employs an RRAM-based, circuit-switched two-dimensional mesh that performs routing in memory. We examine the resulting trade-offs in routing flexibility, hop count, memory requirements, multicast efficiency, and scalability. We further study how the relative efficiency of tree- and mesh-based routing depends on communication locality in spatially-embedded, random, and layered networks. Finally, we discuss routing-aware training as a means of jointly optimizing neural connectivity, task performance, and hardware mappability.
The design of a routing chiplet for the BSS-2 architecture that enables interconnection of multiple BSS-2 units in a 2D mesh topology and can sustain link bandwidth utilization for the use case of surrogate gradient training across a wide range of spike-to-secured traffic ratios with little impact on spike timing jitte...
Findings indicate that the ACORISCVbSNN model has the potential to advance the field of bio-inspired computing, providing a highly accurate, energyefficient, and low-latency system for real-world use.
Yamini Devi Ykuntam, M. V. Nageswara Rao, Leela Kumari. B.· International Journal of Com...· 0 citations
A GPU-accelerated pipeline for SNN mapping is proposed: a multi-level partitioning scheme is devised around hardware constraints, while placement is initialized through recursive bisection, followed by refinement pulling together strongly connected cores through repeated swaps.
A reconfigurable hybrid ring-shaped architecture (Rhr-NoC) to adapt to the large-scale data transmission patterns within accelerators and design a simulated annealing algorithm tailored to the hybrid ring-shaped architecture, providing a more rational scheme for mapping neural networks onto NoC platforms.
Cheng-Long Sun, Yi-He Zhang, Yajun Liu et al.· Journal of King Saud Univers...· 0 citations
This work introduces MITRA, a reconfigurable magnetic tunnel junction-based in-memory architecture that leverages stochastic computing (SC) to implement a broad class of transcendental and nonlinear functions directly within memory.
Farzad Razi, M. Moghadam, M. Najafi et al.· International Symposium on L...· 0 citations
The 194M-parameter model is implemented on an Alveo U50C FPGA using digital fixed-point arithmetic and on an ARM CPU using sparse integer execution to connect event sparsity to omitted computation and data movement in SymbolicLight V2.
Ting Liu· 0 citations
We use cookies to run the site and, with your consent, for analytics and to show ads.
See our Cookie Policy.