This work introduces the first verification framework that jointly analyzes a pseudorandom number generator— specifically, but not limited to, a linear feedback shift register—and a masking scheme, in the d-probing model, in the d-probing model.
Abstract
Masking is a widely adopted countermeasure to protect cryptographic implementations from side-channel attacks. Subsequent research has focused on designing masking schemes and formally proving their security, notably through the development of automated tools, within models abstracting the reality of a sidechannel analysis. These designs rely on an external source of randomness; however, there is currently no consensus on the choice of (pseudo-)random number generators for masking. To the best of our knowledge, existing formal proofs for masking security do not consider particular choices of random number generators, but rather assume that they yield uniformly distributed and independent random variables. In that context, we introduce the first verification framework that jointly analyzes a pseudorandom number generator— specifically, but not limited to, a linear feedback shift register—and a masking scheme, in the d-probing model. Our framework relies on the Walsh-Hadamard transform by drawing on techniques from linear cryptanalysis, which we extend to the robust probing model. We demonstrate our method on 4-bit and 8-bit S-boxes, provide a detailed analysis of the formal verification outcomes, and corroborate the findings with practical evaluations on an FPGA.
This work focuses on detecting (low-level) vulnerabilities in masked FPGA designs through experimental and tool-assisted evaluation and shows how to formally abstract, unveil, and mitigate such leakages, thereby enabling a security-aware FPGA design flow that spans from the behavioral to the physical level.
Nicolai Müller, Daniel Lammers, Simon Osterheider et al.· IACR Cryptology ePrint Archi...· 0 citations
This work focuses on detecting (low-level) vulnerabilities in masked FPGA designs through experimental and tool-assisted evaluation and shows how to formally abstract, unveil, and mitigate such leakages, thereby enabling a security-aware FPGA design flow that spans from the behavioral to the physical level.
Nicolai Müller, Daniel Lammers, Simon Osterheider et al.· IACR Transactions on Cryptog...· 0 citations
This work presents a low-latency, low-randomness, first-order OPINI gadget applicable to arbitrary Boolean functions, denoted as GOM, and proposes OTSM, which is also a generic, low-latency first-order OPINI gadget.
Li-Xuan Wu, Yan-Hong Fan, Guo-Wei Liu et al.· IACR Transactions on Cryptog...· 0 citations
This work proposes two countermeasures in the white-box setting by performing the first formal study of the combinations of existing countermeasures and demonstrating that applying Dummy Shuffling then ISW masking to a circuit carries algebraic, correlation, and filtering security - necessary conditions to withstand st...
Alex Charlès, A. Udovenko· IACR Transactions on Cryptog...· 0 citations
A rigorous security and correctness analysis on Falcon-M, a lightweight signature scheme, reveals that removing the NTRU trapdoor breaks the essential computational asymmetry, causing the verification equation to degenerate into a publicly solvable linear system.
This work proposes CCHPC1.1, an arbitrary-order masked gadget construction that improves Constant-Cycle Hardware Private Circuits (CCHPC) while preserving security in the Robust but Relaxed (RR) d-probing model and under the Probe- Isolating Non-Interference (PINI) composability notion.
Daniel Lammers, Lukas Weber, A. Moradi· IACR Transactions on Cryptog...· 0 citations
We use cookies to run the site and, with your consent, for analytics and to show ads.
See our Cookie Policy.