Breaking the Migration Barrier: Hardware-Software Co-Designed Translation Coherence for Tiered Memory

Abstract

The emergence of novel memory interconnects and devices, such as Compute Express Link (CXL), has driven modern memory systems toward deeply tiered architectures, making page migration crucial for optimizing performance. However, this massive volume of memory page migration incurs significant overhead. Each migrated page requires updating Page Table Entries (PTEs) and invalidating stale translations. Because these frequent migrations involve non-contiguous memory pages, conventional TLB shootdowns incur a significant performance cost. They rely on expensive inter-processor interrupt (IPI) broadcasts and cause severe pipeline disruptions, acting as a practical barrier to aggressive memory migration. To mitigate this translation maintenance overhead, we propose Direct (DIRectory-Enhanced Coherent Translations), a hardware-software co-designed approach that specializes translation coherence specifically for the memory migration path. Through the Translation-Coherent PTE (TC-PTE) structure and a PTE-aware directory controller working in tandem, Direct eliminates conventional TLB shootdowns and reduces execution time by up to 20% in tiered memory systems.